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[VHDL-FPGA-Verilog] lpm_mul

Description: ８＊８的乘法器verilog源代码,经过编译仿真的，绝对真确，对初学者很有帮助-8* 8 Multiplier verilog source code, compiled simulation, absolute authenticity, helpful for beginners
Platform: | Size: 27648 | Author: 刘东辉 | Hits:

[VHDL-FPGA-Verilog] mult8x8

Description: 一个用VerilogHDL语言编写的8X8的乘法器-a Verilog HDL language used in the preparation of the multiplier 8X8
Platform: | Size: 17408 | Author: 胡东 | Hits:

[Embeded-SCM Develop] 16bit_booth_multiplier_STG

Description: verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-modules, testBench the test
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] verilog_multiplier

Description: verilog实现16*16位乘法器，带测试文件-verilog achieve 16* 16 multiplier, with test documents
Platform: | Size: 25600 | Author: zzm | Hits:

[Embeded-SCM Develop] verilog.HDL.examples

Description: 许多非常有用的 Verilog 实例: ADC, FIFO, ADDER, MULTIPLIER 等-many very useful Verilog examples : ADC, FIFO, ADDER, MULTIPLIER etc.
Platform: | Size: 188416 | Author: 张驰 | Hits:

[VHDL-FPGA-Verilog] GFEMultiplierTaps

Description: 用于生成GF(2^m)有限域中乘法器的Verilog HDL源文件的C程序-Used to generate GF (2 ^ m) limited domain Multiplier Verilog HDL source file of C program
Platform: | Size: 199680 | Author: ChenQiu | Hits:

[VHDL-FPGA-Verilog] multiple

Description: 介绍了几种常用的乘法器的设计，carry_save_mult，ripple_carry_mult等，压缩包中包含结构流程图，用verilogHDL语言，采用modelsim仿真验证-This paper introduces some commonly used multiplier design, carry_save_mult, ripple_carry_mult such as, compressed package that contains the structure of flow chart, using verilogHDL language, using ModelSim simulation
Platform: | Size: 266240 | Author: yaoyongshi | Hits:

[VHDL-FPGA-Verilog] 64

Description: 64位乘法器，超前进位的，大家看看，通过仿真的，verilog的-64-bit multiplier, bit-ahead, let us look at the adoption of simulation, verilog of
Platform: | Size: 37888 | Author: | Hits:

[Books] 32bits_float_muliplier

Description: 32位浮点乘法器的设计，讲的挺好的，供参考啊-32-bit floating-point multiplier design, speak very good, and for reference ah
Platform: | Size: 97280 | Author: downloader | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: booth乘法器： 16*16有符号乘法器，Booth编码，简单阵列，Ripple Carry Adder-booth multiplier:
Platform: | Size: 3072 | Author: chenyi | Hits:

[VHDL-FPGA-Verilog] 8bit_adder_AND_4x4_Multiplier

Description: 位加法器的verilog程序与4×4 乘法器的verilog描述-Verilog-bit adder of the procedures and 4 × 4 multiplier verilog description! ! !
Platform: | Size: 1024 | Author: mhb | Hits:

[VHDL-FPGA-Verilog] verilog

Description: verilog语言例题集锦 包含加法器，乘法器，串并转换器等verilog源代码-Example Collection contains verilog language adder, multiplier, and converters, such as string verilog source code
Platform: | Size: 113664 | Author: 刘佳扬 | Hits:

[VHDL-FPGA-Verilog] 8by8multiplier

Description: Verilog HDL for 8*8 multiplier-Verilog HDL for 8*8 multiplier..
Platform: | Size: 49152 | Author: VINOD | Hits:

[VHDL-FPGA-Verilog] floating-point-multiplier

Description: verilog implementation of the floating point multiplier
Platform: | Size: 1024 | Author: ramtin | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 介绍了一种64位子字并行乘法器的设计。根据不同的操作模式可以完成普通模式操作即64bit*64bit乘法操作，又可完成子字并行操作模式，即4个16bit*16bit乘法操作。-Introduced a 64-seat word parallel multiplier design. Depending on the operating mode Normal mode operation can be done that 64bit* 64bit multiplication operations, but also to complete the sub-word parallel operation mode, that is, four 16bit* 16bit multiplication operation.
Platform: | Size: 99328 | Author: 余娅 | Hits:

[VHDL-FPGA-Verilog] Multiplier

Description: 时序乘法器，verilog编写，速度慢，但消耗资源少，时钟沿到来时，输入/输出1bit数据-Sequential multiplier, verilog written, slow, but consume fewer resources, the clock edge arrives, the input/output 1bit data
Platform: | Size: 209920 | Author: 大兵 | Hits:

[VHDL-FPGA-Verilog] carry-save-multiplier-Verilog-code

Description: 进位存储乘法器Verilog代码,该乘法器的显著特点是其性能取决于使用的硬件而与数据长度无关.-carry save multiplier Verilog code
Platform: | Size: 1024 | Author: zhang chunhui | Hits:

[VHDL-FPGA-Verilog] booth

Description: radix 2 booth multiplier verilog code
Platform: | Size: 1024 | Author: Hanumantha Reddy | Hits:

[MiddleWare] Serial-parallel-multiplier-verilog-design

Description: Serial parallel multiplier verilog design source code
Platform: | Size: 27648 | Author: dorababugfree | Hits:

[VHDL-FPGA-Verilog] Low Power Multiplier Verilog

Description: Low Power Multiplier Verilog
Platform: | Size: 2488 | Author: gsrwork2017@gmail.com | Hits:
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